Today's semiconductor technology has been advancing in a direction that requires ever increasing numbers of interconnections with integrated circuits. Typically a large number of integrated circuits are formed on a silicon wafer, then are sliced into individual integrated circuit dies (or chips). Each die is then packaged and used.
Electrical connections to the dies are made in one of a few ways. In one type of package, a die-receiving area (or die receiving cavity) is provided in the package to receive an integrated circuit die. A number of conductive lines (traces or leads) whose outer ends are electrically connected to pins or leads on the package extend inward towards the die receiving area, usually in a radial pattern, stopping just short of the periphery of the die. The die has a number of "bond pads" for the purpose of making electrical connections with the inner ends of the conductive lines, and is mounted such that the bond pads are exposed. The inner ends of these conductive traces or leads are disposed such that they form an array of connection points surrounding the die. Very thin "bond wires" (usually formed of aluminum or gold) are then used to connect the connections points on a one-for one basis with the bond pads on the integrated circuit die. Each bond wire has an "approach angle" to the die. After mounting, the area or cavity containing the die and the bond wires is usually sealed with a cover or an encapsulant to protect the die and the bond wires from ambient moisture or physical damage.
In another type of package, exemplified by Tape Automated Bonding (TAB) packaging, a lead frame is provided having a plurality of conductive leads (sometimes with a tape backing). The lead frame has a die-receiving area, where the semiconductor die is mounted. The leads typically approach and enter the die-receiving area in a radial pattern, with their inner ends extending within the periphery of the die. The die is provided with a pattern of "bond pads". The inner ends of the leads and/or the bond pads are typically provided with solder (or gold) bumps. The die is mounted such that the bond pads align with and make electrical contact with the inner ends of the leads. Evidently, in TAB, or other similar techniques of connecting dies to leads (or traces), bond wires are not employed.
Often, an integrated circuit die may be used in one of several different packages. For example, the same die may be packaged in a plastic or ceramic DIP package (dual inline package), a leadless chip carrier (LCC), a plastic leaded chip carrier (PLCC), etc.. While these packages all have a die-receiving area and conductive traces, the arrangement of conductive traces in the die-receiving area may be slightly different from one package to another. As a result, the approach angle of a bond wire (e.g.) extending to any given bond pad on the die from a corresponding conductive trace may vary somewhat from package to package.
As mentioned before, "conductive traces" are generally printed traces on a ceramic substrate or on a printed circuit board. "Conductive leads" are usually conductors in a lead-frame, such as in a TAB or plastic-molded package. For the purposes of this specification, the term "conductive lines" will be used hereinafter to refer collectively to conductive leads, conductive traces, and bond wires.
FIG. 1 shows a portion of a typical semiconductor device package 100 of the prior art. A die 106 is mounted in a die-receiving area 104. Around the periphery of the die-receiving area 104 is a raised surface 102 with a number of conductive traces 110.
These traces 110 are shown along only one side of the die, for illustrative clarity, but are usually disposed along all (four) sides of the die-receiving area 104. A series of square bond pads 108 are arranged along the edges of the die. Again, FIG. 1 shows bond pads along only one edge of the die for illustrative clarity, but bond pads are usually provided along all of the edges of the die, on the "top" (circuit element containing) surface of the die just within the edges of the die. Bond wires, e.g., 112a, 112b, 112c, 112d and 112e, connect respective conductive traces 110 (e.g., 110a, 110b, 110c, 110d and 110e) to respective bond pads 108 on a one-to-one basis. The conductive traces approach the die 106 in a generally radial pattern (fanned-out, or fanned-in pattern), such that the "approach angles" of conductive traces and bond wires closest to an end of die edge 118 (e.g., 110d, 112d, 110e, and 112e) are the furthest off-perpendicular, while the approach angles of conductive traces and bond wires nearest the center (midpoint) of the die edge 118 (e.g. 110a and 112a) are substantially perpendicular to the edge 118, with the off-perpendicular component of approach angles generally increasing with the offset from the midpoint of the die edge. A centrally located conductive trace 110a and bond wire 108a approach the die such that their approach angle (as shown by dashed line 114) is substantially perpendicular to the edge 118 of die 106. Another conductive trace 110b and bond wire 112b, located three traces (and bond wires) away from the centrally located conductive trace 110a (and bond wire 112a), approaches the die 106 at an off-perpendicular angle 43. Yet another conductive trace 110c and bond wire 112c, located nine traces (and bond wires) away from the centrally located conductive trace 110a (and bond wire 112a), approach the die at an off-perpendicular angle .phi..sub.9 (greater than .phi..sub.3).
FIG. 2 shows a more detailed view of the die 106. A typical bond wire 112 is shown attached to a typical square bond pad 108. An inter-pad spacing of "d" is shown, between bond pads. The bond wire 112 enters the pad area at an approach angle .theta.. The contact area ("footprint") 220 formed by the bond wire 112 with the bond pad 108 is generally elliptical. This is typical of contact footprints between bond wires and bond pads which usually have an elongated shape, with the "elongated dimension" (or "major axis" of the shape, defined hereinbelow) substantially aligned with the approach angle (.theta.).
Typically, prior art bond pads are square, as shown in FIGS. 1 and 2, and are capable of receiving bond wires over a wide range of approach angles, since a bond pad is typically much larger (e.g., in overall area) than the contact footprint formed by the bond wire (or, for example, by an analogous conductive lead in a TAB package).
As stated hereinabove, there is a great deal of pressure in modern integrated circuit technology to provide greater numbers of interconnections (I/O) to integrated circuit dies. This, of course, requires a commensurate increase in the number of bond pads disposed about the periphery of the die. As mentioned hereinabove, there is typically a required minimum inter-pad spacing "d" between adjacent pads to minimize the possibility of shorting or coupling between adjacent bond pads or bond wires (or conductive leads). And, it virtually goes without saying, that the size of bond pads cannot readily be reduced. However, there is a finite, limited amount of space (linear area) along the edges of an integrated circuit die for accommodating bond pads. This evidently limits the number of bond pads that can be arranged along the edges of the die. One approach to increasing the number of bond pads, and hence the number of connections that can be made to the die, is to provide multiple (e.g., two) rows of bond pads along the edges of the die, but this approach would require bond wires to cross over one another, creating a serious risk of a short circuit, even if the rows of bond pads were staggered. (Such a multiple row approach is somewhat inapposite for TAB.) This problem is especially poignant in cases where there is a wide range of approach angles to bond pads possible for different packages.
The present invention is also concerned with the formation (structure) of the bond pad itself, irrespective of the approach angle or I/O count (number of bond pads that fit along the edge of a die) situations discussed above.
Integrated circuit devices comprise a semiconductor die having a variety of diffusions and overlying layers forming circuit elements, gates and the like. Generally, the penultimate layers fabricated on the die are conductive metal layers ("M") having patterns of conductive lines. (These conductive lines are internal to the die, and should not be confused with the leads and traces discussed hereinabove, which are external to the die.) Two or more metal layers ("M1", "M2", etc.) are separated by a dielectric layer of inter-layer dielectric (ILD). For purposes of this discussion, it is assumed that there are two conductive layers, a layer designated "M1", and a layer designated "M2". An ILD layer overlies the M1 layer, and the M2 layer overlies the ILD. Typically, a topmost passivation layer is applied over the M2 layer. Openings through this passivation layer expose areas of the M2 layer. These exposed areas are termed "bond sites". The "bond pad" per se is the bond site, and the underlying M2/ILD/M1 structure. Connections to the die, hence to the circuitry contained on the die, are effected with these exposed areas (i.e., bond pads). For example, bond wires may be bonded directly to the bond sites (pads), or solder or gold bumps may be formed on the bond sites for tape-automated bonding to the die, or gold balls may be formed on the exposed areas for flip-chipping the die to a substrate. This is all well known.
As mentioned above, the bond pad is ultimately bonded to, whether with a bond wire or the like (e.g., solder or gold bumps). These various processes typically impart mechanical and or thermal energy directly onto the bond pad, especially in the contact area. It has been observed that these bonding processes can cause the bond pad to delaminate (lift) from the underlying surfaces of multiple metal layers and oxide. This bond pad lift problem can happen in all different kinds of bonding technology, such as aluminum wire bond, gold ball bonding, gold bump bonding, and others. This bond pad lift problem can become exacerbated when there is layer of barrier metal, such as titanium (Ti), titanium nitride (TIN), Titanium-Tungsten (TiW), and the like, under the bond pads. Bond pad lift is very undesirable, and can result in potential problems in both assembly (packaging) yield and device reliability.
In the past, efforts to alleviate bond pad lift have been directed to: (1) adjusting bonding process parameters to minimize the thermal and/or mechanical shock to the bond pad; and (2) optimizing the barrier metal layer materials and deposition technology. These efforts have met with only partial success, and impose undesirable constraints (i.e., a narrow window of process parameters) on the bonding process.